In a semiconductor memory device, a cell field consisting of a plurality of memory cells and a matrix of column and row supply lines or word and bit lines, respectively, is usually built up. The actual memory cell is positioned at the crosspoints of the supply lines that are made of electroconductive material. The column and row supply lines or word and bit lines, respectively, are each electrically connected with the memory cell via an upper or top electrode and a lower electrode or bottom electrode. To perform a change of the information content in a particular memory cell at the addressed crosspoint, or to recall the content of the memory cell, the corresponding word and bit lines are selected and impacted either with a write current or with a read current. To this end, the word and bit lines are controlled by appropriate control means.
A plurality of kinds of semiconductor memories are known, e.g. a RAM (Random Access Memory) comprising a plurality of memory cells that are each equipped with a capacitor which is connected with a so-called selection transistor. By selectively applying a voltage at the corresponding selection transistor via the column and row supply lines, it is possible to store electric charge as an information unit (bit) in the capacitor during a write process and to recall it again during a read process via the selection transistor. A RAM memory device is a memory with optional access, i.e. data can be stored under a particular address and can be read out again under this address later.
Another kind of semiconductor memories are DRAMs (Dynamic Random Access Memory) which comprise in general only one single, correspondingly controlled capacitive element, e.g. a trench capacitor, with the capacitance of which one bit each can be stored as charge. This charge, however, remains for a relatively short time only in a DRAM memory cell, so that a so-called “refresh” must be performed regularly, e.g. approximately every 64 ms, wherein the information content is written in the memory cell again.
Contrary to this, the memory cells of so-called SRAMS (Static Random Access Memories) usually comprise a number of transistors each. In contrast to DRAMs, no “refresh” has to be performed in the case of SRAMs since the data stored in the transistors of the memory cell remain stored as long as an appropriate supply voltage is fed to the SRAM. Only in the case of non-volatile memory devices (NVMs), e.g. EPROMs, EEPROMs, and flash memories do the stored data remain stored even when the supply voltage is switched off.
The presently common semiconductor memory technologies are primarily based on the principle of charge storage in materials produced by standard CMOS (complement metal oxide semiconductor) processes. The problem of the leaking currents in the memory capacitor existing with the DRAM memory concept, which results in a loss of charge or a loss of information, respectively, has so far been solved insufficiently only by the permanent refreshing of the stored charge. The flash memory concept underlies the problem of limited write and read cycles with barrier layers, wherein no optimum solution has been found yet for the high voltages and the slow read and write cycles.
Since it is intended to accommodate as many memory cells as possible in a RAM memory device, one has been trying to realize them as simple as possible and on the smallest possible space, i.e. to scale them. The previously employed memory concepts (floating gate memories such as flash und DRAM) will, due to their functioning that is based on the storing of charges, presumably meet with physical scaling limits within foreseeable time. Furthermore, in the case of the flash memory concept, the high switching voltages and the limited number of read and write cycles, and in the case of the DRAM memory concept the limited duration of the storage of the charge state, constitute additional problems.
As approaches for solving these problems, so-called CBRAM (CB=Conductive Bridging RAM) memory cells have recently become known in prior art, in which it is possible to store digital information by a resistive switching process. The CBRAM memory cell may be switched between different electric resistance values by bipolar electric pulsing. In the simplest embodiment, such an element may be switched between a very high (e.g. in the GOhm range) and a distinctly lower resistance value (e.g. in the kOhm range) by applying short current or voltage pulses. The switching rates may be less than a microsecond.
In the case of CBRAM memory cells, an electrochemically active material, e.g. a so-called chalcogenide material of germanium (Ge), selenium (Se), copper (Cu), sulphur (S), and/or silver (Ag) is present in a volume between a first electrode or top electrode and a lower electrode or bottom electrode, for instance, in a GeSe, GeS, AgSe, or CuS compound. The abovementioned switching process is, in the case of the CBRAM memory cell, based on principle on the fact that, by applying appropriate current or voltage pulses of specific intensity and duration at the electrodes, elements of a so-called deposition cluster continue to increase in volume in the active material positioned between the electrodes until the two electrodes are finally bridged in an electroconductive manner, i.e. are electroconductively connected with each other, which corresponds to the electroconductive state of the CBRAM cell.
By applying correspondingly inverse current or voltage pulses, this process may be reversed again, so that the corresponding CBRAM memory cell can be returned to a non-conductive state. This way, a “switching over” between a state with a higher electroconductivity of the CBRAM memory cell and a state with a lower electroconductivity of the CBRAM memory cell may be achieved.
The switching process in the CBRAM memory cell is substantially based on the modulation of the chemical composition and the local nanostructure of the chalcogenide material doped with a metal, which serves as a solid body electrolyte and a diffusion matrix. The pure chalcogenide material typically has a semiconductor behavior and has a very high electric resistance at room temperature, said electric resistance being by magnitudes, i.e. decimal powers of the ohmic resistance value higher than that of an electroconductive metal. By the current or voltage pulses applied via the electrodes, the steric arrangement and the local concentration of the ionically and metallically present components of the mobile element in the diffusion matrix is modified. Due to that, the co-called bridging, i.e. an electrical bridging of the volume between the electrodes of metal-rich depositions, may be caused, which modifies the electrical resistance of the CBRAM memory cell by several magnitudes in that the ohmic resistance value is reduced by several decimal powers.
The surfaces of vitreous GeSe layers of the chalcogenide material that are deposited by means of sputtering methods have an amorphous structure and frequently contain superfluous selenium that is poorly bound with respect to the valency bond with germanium. In a method that his known from the document U.S. 2003/0155606, a tempering process is performed at 250° C. in an oxygen atmosphere to oxidize the selenium at the layer surface of the GeSe layer and to evaporate it. The disadvantage of this method consists in that the entire memory device is heated with this tempering, so that an undesired modification of the layer characteristics or interface interdiffusions may occur.
Moreover, the thermal energies that are employed with this method for dissolving the selenium agglomerations lie within the meV range. In this energy range, however, only those selenium atoms that are very weakly bound, i.e. that are practically unbound, can be deactivated or solved out. Weakly bound selenium atoms or selenium atoms that are conglomerated like clusters cannot be removed with this known method and thus lead to the formation of AgSe conglomerates in the Ag doping and electrode layer.
In another method known from U.S. 2003/0045049, the treatment of the surface with an oxygen or hydrogen plasma or other chemicals is suggested so as to generate a passivation layer on the GeSe layer. The only object of this method, however, is to form a passivation layer at the surface of the Ag-doped GeSe layer. The oxide passivation layers that are formed with different oxygen treatments tend to crystallize at low temperatures already. The oxide layer therefore does not behave chemically inert to the Ag electrode, i.e. the formation of silver oxide may take place at the interface of the Ge oxide layer with the Ag electrode, which is of disadvantage for the function of the CBRAM memory cell. Furthermore, the passivation layer that has to be sufficiently chemically compact to be able to prevent the formation of conglomerates also forms an electronic barrier modifying or preventing the contact to the top electrode and thus the switching behavior.